A switching amplification circuit is known as a class-D amplifier, and allows for high-efficiency amplification of an input signal when used together with a PWM modulation circuit, a synchronous delta-sigma modulation circuit, and an asynchronous delta-sigma modulation circuit. A switching amplification circuit using a delta-sigma modulator is disclosed in Non-patent Document 1 (“A delta-sigma modulator for 1-bit digital switching amplifier”, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, pp 177-180) and in Non-patent Document 2 (“A delta-sigma modulator for a 1-bit digital switching amplifier”, IEEE Journal of Solid-State Circuits, Vol. 40, No. 9, September 2005). The use of such a high-order single-loop 1-bit delta-sigma modulator for modulating a signal sent to the switching amplification circuit allows realization of a switching amplification circuit which has a high oscillation threshold value, and which allows for a low distortion, and which has a great dynamic range. Here, as described in page 1865 and FIG. 1 of Non-patent Document 2, the oscillation threshold value refers to the maximum amplitude ratio of (i) the amplitude of a sine wave component contained in a 1-bit output of the switching amplification circuit to (ii) the amplitude of the 1-bit output, when the delta-sigma modulator does not oscillate. The sine wave component corresponds to a sine wave signal which is supplied to the switching amplification circuit and which has a frequency falling within a desired band.
However, for the purpose of realizing high performance, the delta-sigma modulator needs to operate at a sampling frequency sufficiently higher than the desired signal band (e.g., an audio signal band of 0 Hz to 20 kHz). In Non-patent Document 1, the over-sampling ratio (OSR) is 128, and the sampling frequency is 5.6 MHz. The over-sampling ratio refers to a ratio of the sampling frequency to a frequency falling within a band twice wider than the desired signal band.
A delta-sigma modulator similar to the arrangement of Non-patent Document 1 was checked by simulation. As a result, the average switching rate of the delta-sigma modulator was found to range from 2M times/sec to 4M times/sec. Here, the average switching rate refers to a sum of (i) the number of rising edges, per unit time, of a 1-bit output of either the delta-sigma modulator or the switching amplification circuit, and (ii) the number of falling edges, per unit time, of the 1-bit output thereof. An increase in the average switching rate causes a charge current and a through current to proportionately flow through a power switch stage constituting the switching amplification circuit. This causes an increase in power consumption. Therefore, it is difficult for the switching amplification circuit of Non-patent Document 1 to realize high efficiency (high power efficiency) in terms of the electric power.
In order to solve the foregoing problems, a method for reducing the average switching rate has been proposed (e.g., see Japanese Unexamined Patent Publication Tokukaihei 11-266157/1999 (published on Sep. 28, 1999; hereinafter, referred to as “Patent Document 1”). FIG. 19 is a block diagram illustrating a switching amplification circuit 101 that operates in accordance with the method. The switching amplification circuit 101 includes a subtracter 102, a loop filter 103, a comparator 104, a pulse width holding circuit 105, and a power switch stage 106.
The subtracter 102 calculates a difference between an input signal X and an output signal V. The input signal X and the output signal V are sent to gain stages B1, respectively. The gain stages B1 multiplies the input signal X and the output signal V by a gain B1. Then, the signals thus multiplied are sent to the subtracter 102. The loop filter 103 includes: seven time-discrete integrators I1 to I7; an adder S, which calculates a sum of respective outputs of the integrators; gain stages A1 to A7; gain stages C1 to C6; and gain stages G1 to G3. The loop filter 103 processes an output of the subtracter 102. The comparator 104 serves as a 1-bit comparator that converts an output signal Y1 of the adder S into a 1-bit signal and that outputs the 1-bit signal as an output signal Y2.
The gain stages A1 to A7 sequentially multiply the outputs of the integrators I1 to I7 by gains A1 to A7, respectively. Then, the gain stages A1 to A7 send the multiplied outputs to the adder S. The gain stages C1 to C6 sequentially multiply the outputs of the integrators I1 to I6 by gains C1 to C6, respectively. The gain stages G1, G2, and G3 sequentially multiply the outputs of the integrators I3, I5, and I7 by gains G1, G2, and G3, respectively. Moreover, the integrator I2 receives a difference between an output of the gain stage G1 and an output of the gain stage C1. The integrator I4 receives a difference between an output of the gain stage G2 and an output of the gain stage C3. The integrator I6 receives a difference between an output of the gain stage G3 and an output of the gain stage C5.
The pulse width holding circuit 105 converts, into a pulse signal having a certain width or greater, the 1-bit signal which is sent from the comparator 104, and which has a minimum pulse width. Then, the pulse width holding circuit 105 outputs the pulse signal as an output signal Y3. The power switch stage 106 amplifies the output signal Y3 supplied from the pulse width holding circuit 105, so as to transmit the output signal V to a load. Further, the power switch stage 106 feeds the output signal V back to the loop filter 103 via the subtracter 102.
The arrangement of FIG. 19 is basically the same as that of Non-patent Document 1, but is different from that of Non-patent Document 1 in that the arrangement of FIG. 19 has the pulse width holding circuit 105 provided between the comparator 104 and the power switch stage 106. The pulse width holding circuit 105 is a circuit for converting, into a 1-bit signal having a minimum pulse width of 2×Ts, the 1-bit signal Y2 which is sent from the comparator 104 and which has a minimum pulse width of Ts.
The arrangement of FIG. 19 makes it possible to reduce the average switching rate by approximately half, as compared with the case where no pulse width holding circuit 105 is provided. However, the reduction in the average switching rate brings about only a minor effect. Further, the use of the pulse width holding circuit 105 inevitably reduces the oscillation threshold value. Accordingly, the following demand arises: the average switching rate should be reduced, but the oscillation threshold value should not be reduced.
As such, the switching amplification circuit described in Patent Document 1 cannot sufficiently reduce the average switching rate. This makes it impossible to realize a switching amplification circuit attaining high power efficiency. Further, even though the average switching rate can be reduced slightly, the oscillation threshold value is accordingly reduced. This inevitably reduces the maximum output power of the switching amplification circuit.